Cache memory is a component that is used to improve performance by storing data so that future requests for that data can be served faster. The data that is stored within a cache memory might be values that have been computed earlier or duplicates of original values that are stored elsewhere. If requested data are contained in the cache (referred to as a cache hit), the request can be served by simply reading from the cache memory, which is comparably faster. Otherwise, if the requested data is not contained in the cache (referred to as a cache miss), the data has to be recomputed or fetched from its original storage location such as the main memory, which is comparably slower. Hence, the more requests can be served from the cache, the better the overall system performance is.
To ensure the correctness of the cache access, the cache address need to be verified to ensure it is not corrupted. A cache memory includes a data cache memory and a tag cache memory, wherein the addresses of the cached data saved in the data cache memory are saved in the tag cache memory, which stores addresses. Accordingly, when a request for accessing the cached data is made, the address in the request will be verified by comparing the address with the data (referred to as a tag) saved in the tag cache memory. FIG. 1 illustrates a block diagram of a conventional circuit for the verification of the tag. Tag cache memory array 100 stores tags, which are the addresses of the cached data. For each of the tags, for example, tag tag[23:0], a parity bit of tag tag[23:0] is also saved. In the tag verification, the address denoted as phy_address, which address may be used in a central processing unit (CPU) instruction, is provided. Comparator 102 compares address phy_address and tag tag[23:0] bit-by-bit to generate a read-hit (rd_hit) bit. If address phy_address is identical to tag tag[23:0], the rd_hit bit is true. Otherwise, it is false.
The rd_hit bit is provided to parity-check unit 104 to generate a read-parity (rd_parity) bit, which indicates whether the parities of the tag tag[23:0] and the address phy_address are the same as the parity of tag tag[23:0] when it is saved. The rd_parity bit may be calculated as tag[23] ^ tag[22] ^ . . . tag[1] ^ tag[0] ^ parity, wherein values tag[0] through tag[23] are the bits of tag tag[23:0], and the bit “parity” is the parity bit of tag tag[23:0], which parity bit is read from tag cache memory array 100. The symbol “^” represents an exclusive-OR operator. Parity-check unit 104 also receives a valid bit from tag cache memory array 100, wherein the valid bit indicates whether tags are valid or not, and if valid bit is true, the generated rd_hit bit and rd_parity bit are outputted. Otherwise, rd_parity bit is set to false.
The time for the tag verification is critical to the performance of the cache memory. It was estimated that reading tag tag[23:0], the parity bit, and the valid bit from tag cache memory array 100 may take up to 300 pico-seconds (ps). Parity-check unit 104 may take up to 200 ps to process tag tag[23:0], the valid bit, the rd_hit bit, and the parity bit. Comparator 102 may take up to 125 ps to generate rd_hit bit, and the “AND” operation of the rd_hit bit and the parity bit may take 20 ps. Accordingly, the total time for the tag verification takes 300+200+20=520 ps. The 125 ps used by comparator 102 is not considered since it is in the same time frame used by parity-check unit 104 (200 ps).